Traditional memory error correction schemes have involved approaches for detecting errors using an error detecting code and correcting the detected errors using an error correcting code. These traditional approaches often insert parity bits for each word of a page of the memory to detect single-bit errors via the error detection capacity of an error correcting code, and thereafter correct the detected single-bit errors via the error correction capacity of the error correcting code. These approaches are often tried to improve the reliability of the content of a page of memory, for instance.
Unfortunately, these approaches have proved limiting as their techniques are often overly burdensome in their requirements for overhead and power consumption. For instance, substantial overhead burdens result for NOR Flash Memories, as all of the words of a page of memory and/or each added detection parity bit per word is required to be read as part of the error detection scheme to detect an error per word. These techniques are also inadequate for memories having read operations which differ from their programming (i.e., write) operations, such as the NOR Flash Memory. Similarly, attempts to overcome the inefficiencies by various improvement schemes have also proven inadequate.